“[0022] Therefore, there exists a need for a DC-DC converter that is simultaneously compact (including optimally fabrication of all active and passive components on a single semiconductor die), low in cost, and highly efficient even at small ratios of output to supply voltage and low output current. [0023] It is desirable to have a method and apparatus for protecting switching elements of a converter from transient voltages to allow fast low-loss switching operations without degradation of reliability.”
“[0067] It should be noted that voltage spikes will occur in any converter that has fast switching transitions without added shunt capacitance around the switches, irrespective of whether the switching elements are stacked NMOS switches, or any other type of switch that includes, for example, PMOS transistors, a single PMOS transistor, a single NMOS transistor, or any other fast switching device. Additionally, while the detailed behavior shown in Figure 18 may be specific to the described embodiments, the general phenomena of excessive voltage excursions (spikes) and ringing will occur any time a fast switching transition without added shunt capacitance is used in a converter.”
“[0068] Clearly, it is desirable to provide spike protection circuitry for the series and shunt switch elements of any DC-DC converter employing fast switching transitions as described above. Ideally, the spike protection includes capacitive elements between previously described first voltage supply and second voltage supply. For an embodiment, the spike protection circuitry includes a transmission line having minimal parasitic inductances, thereby minimizing the impedance of the transmission line.”
“[0078] A solution to this problem can be found by further subdividing switching elements of the switching circuitry into segments (switching block segments) connected in parallel, such that each segment carries a portion of the total output current, and further partitioning the protection circuit Csp - Rsp into separate segments, each protecting one of the switching block segments.”
“In an embodiment, the protection circuitry is further subdivided such that a portion of the protection circuit is disposed on each side of the switching circuit segment, and optionally in other convenient locations proximate to the switches themselves. For an embodiment, at least a portion of the voltage spike protection circuitry is located between the plurality of switching block segments. The spike protection circuitry can include charge-storage circuit segments. An embodiment includes each charge-storage circuit segment of the spike protection circuit being located physically closer to the switching block segment it protects than any other switching block segment.”
“… ensure that the voltage across the transistors does not exceed the maximum allowed voltage during the operation of the switched mode regulator circuitry.”
“… the type of degradation that is most relevant to gradual accumulation of damage from stress on the transistor caused by persistent exposure to smaller over-voltages over a long period of time (which ultimately compromises the reliability of the transistor/renders it unable to be controlled effectively).”
“374. … The Skilled Person would have understood that term to refer to arrangements in which the charge storage circuit segments are physically arranged in close proximity to corresponding switching block segments (as discussed in [0077]–[0080] and depicted in Figures 20-22 of the Patent) …”
“107. From my reading of the Patent overall I understand that the core concepts the authors are seeking to present as inventive are: … b. the subdivision of switching circuitry and spike protection circuitry (respectively) into smaller segments or blocks, arranged proximally to one another in a certain physical arrangement (referred to in the claims of the Patent as ‘interleaving’) to minimise parasitic inductance from the associated connections; …”
“In an embodiment, the protection circuitry is further subdivided such that a portion of the protection circuit is disposed on each side of the switching circuit segment, and optionally in other convenient locations proximate to the switches themselves.”
“[39] … Supponor’s argument is an example of a familiar wrong approach to the construction of patent claims. Limitations which are not present in the claim language are not to be read in by reference to examples which appear in the specification. The skilled person reading a patent understands that the examples are simply that. If the claim language is broad – as the term ‘image property’ clearly is – then the claim is correspondingly broad, for good or ill. The fact that the result will be that the claim therefore covers other approaches, different from those in the examples, is not on its own a reason to read the claim in a limited way. In some cases the consequences of different possible constructions e.g. for validity, might be relevant but only if those consequences would be part of the skilled person’s thinking based on the patent and the common general knowledge.”
“Q. Because the outputs are operating in parallel, we know that the switches must operate synchronously so that all the top switches open and close on the same timing and all of the bottom switches open and close on the same timing; yes? A. Yes, if it a Phase I inductor, it has to be. Q. Although it is not shown, the skilled person would know that the gate drive signals for all of the top switches must be connected in parallel and the same for all of the bottom switches; yes? A. Yes, the gate's signals can be connected or you have a driver for each slice, but they are synchronously switched.”
“To determine the feasibility and performance of such monolithic dc-dc converters for 3D power delivery, we developed a fully integrated, two-phase interleaved buck converter with linear feedback control in a 180 nm SiGe BiCMOS process. The converter operates at around 200 MHz switching frequency, …”
“Input capacitors are needed to filter out the discontinuous input current so as to limit the di/dt voltage generated through the parasitic inductance between the input voltage source and the prototype chip.”
“Interleaving is known to cancel the output ripple current in multiphase buck converters; an unexploited benefit of interleaving is that it also reduces input current ripple of multiphase buck converters.”
“The combination of small ripple amplitude and much higher ripple frequency implies that the input filter capacitance required by 10 interleaved converter cells can actually be smaller than that required by a single cell.”
“3D power delivery overcomes the limitations of conventional 2D power delivery architecture by eliminating most of the interconnect parasitics. Fully monolithic dc-dc converters compatible with the 3D platform are capable of meeting the needs of future microprocessors and high-performance ASICs for multiple, dynamically scalable, sub-1V supply voltages. The 3D platform can tolerate less efficient voltage regulators, and can be utilized to achieve more efficient converter design. The proposed cellular converter architecture enables full utilization of the benefits of interleaving to reduce filtering requirements, and is ideally suited for 3D integration.”
“If the prior inventor's publication contains a clear description of, or clear instructions to do or make, something that would infringe the patentee's claim is carried out after the grant of the patentee's patent, the patentee's claim will have been shown to lack the necessary novelty, that is to say, it will have been anticipated. The prior inventor, however, and the patentee may have approached the same device from different starting points and may for this reason, or it may be for other reasons, have so described their devices that it cannot be immediately discerned from a reading of the language which they have respectively used that they have discovered in truth the same device; but if carrying out the directions contained in the prior inventor's publication will inevitably result in something being made or done which, if the patentee's patent were valid, would constitute an infringement of the patentee's claim, this circumstance demonstrates that the patentee's claim has in fact been anticipated. If, on the other hand, the prior publication contains a direction which is capable of being carried out in a manner which would infringe the patentee's claim, but would be at least as likely to be carried out in a way which would not do so, the patentee's claim will not have been anticipated, although it may fail on the ground of obviousness. To anticipate the patentee's claim the prior publication must contain clear and unmistakable directions to do what the patentee claims to have invented: Flour Oxidizing Co. Ltd. v. Carr & Co. Ltd. (1908) 25 R.P.C. 428 at 457, line 34, approved in B.T.H. Co. Ltd. v. Metropolitan Vickers Electrical Co. Ltd. (1928) 45 R.P.C. 1 at 24, line 1). A signpost, however clear, upon the road to the patentee's invention will not suffice. The prior inventor must be clearly shown to have planted his flag at the precise destination before the patentees.”
“A. … The degradation to sudden death is a very small voltage difference, it goes really bad at some point, so you do not want to be in the slow degradation part that is already bad. Q. This degradation, we are talking long-term degradation, we are talking years of operation, not hours or weeks or months? A. It could be ten years, high temperature. Q. Given Sun is a prototype, there is no reason to think that it had undergone product reliability, testing, is there? A. I do not think they did reliability testing, but they did measurements on the chip and it least it worked for a day, I would say. You cannot be close to this breakdown limit, you will really kill your transistors. The difference is tens of millivolts. It is quite, from slow degradation to death, it is a small step.”
“367. I do not think the Skilled Person would have appreciated the issue of spiking and ringing for very high frequency converters at the priority date. However, once they were aware of the issue from the teaching of the Patent they would have considered that the spike protection circuitry proposed by the Patent was an effective solution to the problem.”
“370. Another noteworthy observation that the Skilled Person would also have taken from the Patent is that a dissipative element is needed in the spike protection circuitry for it to be effective. In the ordinary design of the power path for a voltage regulator at the priority date a designer would have sought to minimise the ESR [equivalent series resistance] of interconnects and other components as far as possible. The disclosure of the Patent runs counter to this – i.e. to either intentionally introduce resistive components or to leverage (and not seek to minimise as far as possible) the ESR associated with the capacitive element. The Patent teaches that this dissipative element is required in order to damp the identified high frequency ringing behaviour.”
“80. In my view that Skilled Person would have been very well-aware of the potential issue of voltage spiking and ringing in high frequency switching circuits, including voltage converters. This would have been readily evident, not only: (a) as the simple consequence of absolute fundamentals of electrical engineering; but also (b) because this exact issue had been identified and addressed in other high frequency switching circuits such as the digital logic circuitry of processors (which, as I explained in paragraph 19 above, involved switching at frequencies up to and above 3 GHz by the year 2000); and (c) from discussions of this precise issue in textbooks and other literature in the field before the Priority Date.”
“Q. … Anyone making Sun and thinking about using Sun is going to know that the transistors they use will have a voltage limit? A. Yes. Q. They are not going to want to go over that? A. Generally, no. Q. Even if you were right, and we do not accept that, but even if you are right that Sun does not tell the reader about voltage-spike protection, it is something that the skilled person will have in mind and they will want to avoid voltage spikes on their transistors in the regulator? A. In the very general sense, for of the specific field of on-chip power conversion, people were [not] The word “not” in square brackets does not appear in the transcript. The parties did not agree whether Professor Alarcón said “were very aware” or “were not very aware”. very aware of this; not to say they were not. Q. Let us take those people. Again, we do not accept that, but I understand you have this set of people who do not know that. They are going to test and very quickly find out, are they not, if they have voltage problems, because one tests either for immediate destruction or one tests for ---- A. Yes. Q. You are going to do that, are you not? A. Engineers of a team of a product will do that.”
“Q. You are always going to have a reliability engineer who is going to check whether or not the transistors in your regulator are being harmed? A. Yes, with -- yes, with the difference that these were new transistors, because they were very large. I am aware of the way engineers were stressing with test campaigns, large (indistinct) MOS off-chip in a standalone package, but I do not think there was enough experience to do so with very large transistors on a CMOS chip. But eventually, if this needs to go into a product, of course this needs to be done, of course.”
“86. I do not understand Professor Alarcón to be suggesting that – if he is wrong about the problem of voltage spiking and ringing in high frequency converters not being appreciated by the Skilled Person at the Priority Date – there is anything inventive about using decoupling capacitors per se to address that problem. Doing so is entirely consistent with and obvious from Professor Alarcón’s own description of the function and purpose of decoupling capacitors in paragraph 169 and his explanation that a voltage regulator is required to maintain the output voltage within tolerated limits despite variations that occur at either the input or output ports (paragraphs 176 to 177).”
“‘Voltage regulators’ (also called ‘power regulators’) are a subset of power converters that convert one DC voltage to another DC voltage …”
“A FIVR consists of multiple parallel phases, each with a single associated output inductor. Each such phase is a voltage regulator of the claim.”
“Q. A skilled team is very well aware of both of those and which to use. Whether it is a single phase arrangement or a multi-phase arrangement, will be dependent on their design requirements and what they want, really? A. In a general sense, yes. Time interleaving, power connected, multi-inductor, multi-phase were the natural option for off-chip voltage regulator models because there was the need to provide more current and, in turn, improve the design trade-offs of the output ripple. That was the state of the art. Q. Right. A. A design team would be aware of these things, which one to consider is not going to need a decision, but it is an engineering decision. Q. Yes, and it is within the skill of our team to decide, it is a design consideration more than anything else, is it not? A. It is a design consideration in general terms, yes.”
“The maximum permitted peak transient voltage that can be experienced by the switching transistors whilst still achieving Intel’s target level of reliability is approximately 2.5V.”
“Less than 300 defects per million over the 5-year product lifetime period for the 10nm Representative FIVR.”
“The specific maximum voltage limit that the switching transistors can be exposed before instantaneous destruction is observed is not known, but Intel testing results show that no instantaneous damage to the switching transistors of the 10 nm Representative FIVR was observed for Vccin input voltages up to at least [confidential figure in volts]”
“The mode of degradation most relevant for a 5-year product lifetime reliability assessment for the switching transistors of the 10 nm Representative FIVR is time dependant dielectric breakdown (“TDDB”) of the gate oxide of the NMOS transistors, as a result of the internal gate-drain voltage of the NMOS. With the conservative assumption noted above [footnote], a DC input voltage of 1.8 V (as specified in the PPD), and employing a reliability model for TDDB of the gate oxide of the NMOS transistor, the maximum permitted peak transient voltage to achieve the target reliability of less than [confidential figure] DPM over the 5-year product lifetime period for the 10 nm Representative FIVR is 2.3 V. Assuming a more real-world relationship between the total Vccin input voltage and the internal gate-drain voltage of the NMOS (likely to be in the region of 55%, according to Intel’s analog transistor modelling) the maximum permitted peak transient voltage to achieve the target reliability of less than [confidential figure] DPM over the 5-year product lifetime period for the 10 nm Representative FIVR is approximately 2.5 V.”
“i.e. that 100% of the DC voltage and transient overshoot of the Vccin input voltage will be seen internally as a gate-drain voltage in the NMOS transistor.”
“CPR PD63 7.1 requires that a party seeking to establish any fact by experimental proof conducted for the purpose of litigation must (my emphasis) serve a notice “(1) stating the facts which the party seeks to establish”
“25. It is correct the Defendants Intel has not proposed any ‘corrections’ to the sizing of the transistors used in the Amended R2 Model. The Defendants are not aware of TSMC’s modelling processes and therefore cannot identify the ‘corrections’ to be made to the TSMC’s modelling processes so that they materially reflect the transistor models used in the Amended R2 Model. It is correct that Intel has not provided its own transistor models for use in the Amended R2 Model – such proprietary ‘process technology’ information is of the highest sensitivity and confidentiality to Intel, and cannot be accessed or used outside of Intel’s engineering compute environment, to which access cannot be granted externally, due to being an unacceptable security risk not only for Intel as a global leader in process and chip design, but as a matter of US national security. 26. The Defendants’ position is that provision of Intel’s own transistor models is not necessary in the circumstances. The Defendants are content for the Amended R2 Model to employ TSMC transistor models, or alternatively for ideal switches to be employed (as per the Revised Intel Model), in each case strictly provided that proper account is taken of the parasitic capacitance contributed by Intel’s actual transistors (as determined by Intel from a layout extraction reflecting the parasitics from the switching transistors and power distribution grid to/from those transistors and provided to the Claimant in the Defendants’ R2 Model Question Responses. The use of ideal switches in this respect is a ‘conservative’ or ‘pessimistic’ modelling assumption (i.e. an assumption adverse to the Defendants) in that the properties of ideal switches (which transition from open to closed and vice versa more rapidly than a real switch), are such that they will result in overestimation of the rate of change of current through the relevant parasitic inductances in the network and correspondingly the magnitude of voltage spikes at the input to the switching circuitry.”
“The general tolerances between these simulations and the real world (i.e. difference between nominal parameters ‘pre-silicon’ and ‘post-silicon’ actual characteristics) is in the range of +/- 30%. This is due to variation in component values, package and board manufacturing tolerances, etc as part of the fabrication process.”